1. Field of the Invention
This invention automates the process of determining the distribution of spare gate array cells in random logic macros (RLM) in the design of central processors.
2. Description of Background
The design of today's high speed microprocessor must be logically well-defined. The increased design complexity of leading-edge microprocessors and systems on a chip (SoC) is driving the industry to find better ways to implement the physical and logical designs of chips. The logical design involves gate array cells which can be used as spare logic for physical fixes requiring only higher level changes in the several layers of the chip. Having enough gate arrays in a design may determine if a bug fix is possible in a certain derivation of the design. For this reason it becomes important to maximize the density and efficiency of the placement (utilization) of the cells.
The process of analyzing the distribution of gate array cells is currently done by visual inspection of each macro individually. First a utilization code provides the design team with a fill cell percentage in a random logic macro (RLM). An RLM is a physical entity that includes control logic. It is desirable to know the percentage of the cells in the RLMs in order to determine the congestion by means of optimization criteria. Then the design team visually inspects the RLMs that are flagged as having poor utilization, as determined by the fill cell percentages. The problem with this method is that low utilization does not always equate with an unacceptable distribution of fill cells. Likewise, high utilization does not always equate to an acceptable distribution of fill cells.